1. Field
The present invention relates to a semiconductor package substrate and a method for fabricating the same. More particularly, the present invention relates to a semiconductor package in which a circuit layer formed on the wire bonding pad side is different in thickness from a half-etched circuit layer formed on the ball pad side and which has a connection through hole through which the plating lead lines of the wire bonding pad side and the ball pad side are electrically connected, so that electrical disconnection is prevented when the plating lead line of the wire bonding pad is cut, and a method for fabricating the same.
2. Description of the Related Art
With the evolution of electronics towards slimness, lightness and high performance, a great advance in technology for fine circuit patterns has been recently achieved on BGA package substrates.
Particularly, fine circuit patterns are extensively required in CSP (chip-sized package) products, which have semiconductor chips mounted on BGA package substrates.
In order to better understand the background of the invention, a conventional method of fabricating a semiconductor package substrate will be described with reference to FIGS. 1A to 1H.
As shown in FIG. 1A, a copper clad laminate (CCL) 100 comprising an insulation layer 102 covered with a copper foil 101, which is provided as a base substrate, is drilled to form therein via holes for electric communication between circuit layers. There are a variety of CCLs including glass/epoxy CCLs, heat resistant CCLs, paper/phenol CCLs, CCLs for use in radio frequencies, flexible CCLs (polyimide film) and composite CCLs, which are used according to purpose. For example, glass/epoxy CCLs are suitable for the fabrication of double-sided PCBs and multilayer PCBs.
Then, the opposite sides of the CCL 100 and the inner walls of the via holes are subjected to electroless plating and then to electroplating, as shown in FIG. 1B. Requiring electricity, electroplating cannot be conducted on the insulation layer 102. Usually, an insulator is electroless plated prior to being electroplated. Thus, copper is electroless plated and then electroplated on the insulation layer 102.
Next, a filler is charged in the via holes 103, followed by the formation of an etching resist pattern 105 as shown in FIG. 1C. In regard to the etching resist pattern 105, it is formed using a dry film (D/F) and a circuit pattern printed film (artwork film) on the copper-electroplated substrate.
There are various techniques available for the formation of the resist pattern 105, with a dry film technique prevailing.
A dry film for use in forming the resist pattern, abbreviated to D/F, is usually comprised of a cover film, a photoresist film and a Mylar film. The photoresist film actually serves as a resist.
While being stripped of the cover film, the dry film is applied to a bare PCB. A circuit pattern-printed artwork film is stuck fast onto the dry film, followed by UV irradiation. UV light cannot penetrate through the dry film at the dark portion of the pattern of the artwork film, but penetrates through otherwise portions to cure the exposed portion of the dry film. Then, the substrate is immersed in a developing solution to remove the uncured portions of the dry film while the cured portions remain to form a resist pattern. A 1% sodium carbonate (Na2CO3) or potassium carbonate (K2CO3) solution is suitable as a developing solution.
Afterwards, as shown in FIG. 10, the CCL 100 is treated with an etchant while the etching resist pattern 105 serves as a mask, so as to form a circuit pattern.
Subsequently, the etching resist 105 is removed with a peeling solution such as an NaOH or KOH solution, as shown in FIG. 1E.
All portions of the resulting CCL, except for a wire bonding pad 107, a solder ball pad 108, and the other portions connected to external substrates or chips, are coated with a photo solder resist 106 so as to protect the circuit, as shown in FIG. 1F.
Using a plating lead line, thereafter, the CCL is plated with Ni/Au, with the photo solder resist serving as a plating resist, to form an Ni/Au layer 109, 109′ on the uncoated portions, that is, the wire bonding pad 107, the solder ball pad 108 and the other connection portions, as shown in FIG. 1G. Plating is conducted with Ni and then with Au.
Finally, FIG. 1H shows a package product obtained after the circuit pattern 110 serving as a plating lead line is cut using a router or a dicing process.
In CSP products, ball pitches have continued to decrease from 0.8 through 0.65 and 0.5 then to 0.4 mm. In addition, the balls require an OSP (organic solderability preservative) treatment so as to have a drop resistance the same level as that of substrates for mobile phones. However, the requirement causes contrast techniques to be performed on the substrate, as will be described below.
With reference to FIG. 2, a conventional semiconductor package substrate 210 is shown in a perspective view. As seen, the conventional semiconductor package substrate 210 is divided into a unit region, comprising a semiconductor device mounting portion 211a and an outer circuit pattern 211b, and a dummy region 212.
This conventional semiconductor package substrate requires contrast techniques which are used to keep the circuit layer at a small thickness so as to realize a fine pattern at the side of the wire bonding, but at a large thickness at the side of the balls so as to enable application of OSP and deep etching processes to the balls.